1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and a method for manufacturing the same in which a plurality of insulating films and a plurality of electrode films are alternately stacked.
2. Background Art
Nonvolatile semiconductor memory devices of flash memory and the like conventionally are constructed by two-dimensionally integrating elements on a surface of a silicon substrate. In such a flash memory, the dimensions of each element must be reduced for downsizing to reduce the cost per bit and increase the memory capacity. However, such downsizing in recent years has become difficult in regard to both cost and technology.
Many ideas for three-dimensionally integrated elements are proposed as technology to breakthrough the limitations of increasing the integration. However, three-dimensional devices generally require at least three lithography steps for each layer. Therefore, the cost increases accompanying the increase of lithography steps unfortunately cancels the cost reductions gained by surface area reductions of the silicon substrate; and it is difficult to reduce costs even using three dimensions.
In consideration of such problems, the present inventors have proposed a one-mask patterned three-dimensional stacked memory (for example, refer to JP-A 2007-266143 (Kokai)). In such technology, a stacked body is formed on a silicon substrate by alternately stacking electrode films and insulating films, and then forming through-holes in the stacked body by one-mask patterning. A charge storage layer is formed on a side face of each through-hole, and silicon is filled into the through-hole to form a silicon pillar. A memory cell is thereby formed at an intersection between each electrode film and each silicon pillar.
In such a one-mask patterned three-dimensional stacked memory, charges can be pull out from the charge storage layer to the silicon pillar and charges can be put into the charge storage layer from the silicon pillar to record information by controlling an electrical potential of each electrode film and each silicon pillar. According to such technology, a plurality of electrode films are stacked on the silicon substrate. Thereby, the chip surface area per bit and the cost can be reduced. Moreover, the three-dimensional stacked memory can be constructed by one-mask patterning of the stacked body. Therefore, the number of lithography steps does not increase, and the cost can be prevented from increasing even in the case where the number of stacking increases.